A nonvolatile memory device, known as a flash EEPROM (electrically erasable programmable read only memory), typically includes a memory cell array having memory cells including a floating gate transistor organized as memory blocks. Each of the memory blocks includes strings of the floating gate transistors (i.e., “NAND strings”). The floating gate transistors are connected in series between a string selection transistor and a ground selection transistor that are arranged in each string. A plurality of word lines are arranged so as to be intersected with the NAND strings. Each of the word lines is connected to a control gate of a corresponding floating gate transistor of each NAND string.
Flash memory devices and program methods are discussed in, for example, U.S. Pat. No. 5,568,420, entitled “NONVOLATILE SEMICONDUCTOR MEMORY DEVICE”, U.S. Pat. No. 5,606,527, entitled “METHODS FOR DETECTING SHORT-CIRCUITED SIGNAL LINES IN NONVOLATILE SEMICONDUCTOR MEMORY AND CIRCUITRY THEREFOR”, U.S. Pat. No. 5,661,682, entitled “NONVOLATILE SEMICONDUCTOR MEMORY DEVICE”, U.S. Pat. No. 5,696,717, entitled “NONVOLATILE INTEGRATED CIRCUIT MEMORY DEVICES HAVING ADJUSTABLE ERASE/PROGRAM THRESHOLD VOLTAGE VERIFICATION CAPABILITY”, and U.S. Pat. No. 6,236,594, entitled “FLASH MEMORY DEVICE INCLUDING CIRCUITRY FOR SELECTING A MEMORY BLOCK”, all of which are incorporated herein by reference in their entireties.
Referring to FIG. 1A showing a conventional program process of a flash memory device, program data is loaded in a register of a flash memory device (Block 10). When the program data is loaded, one of memory blocks is selected according to an inputted block address (Block 20). The memory block is selected by supplying a high voltage to a block word line so that a pass voltage and a program voltage are applied to the word lines without a voltage drop. The above-described operation for selecting a memory block is discussed in the above references, and further detailed explanation thereof will be omitted.
After the memory block is selected, a program operation is executed (Block 30). As well known to one skilled in the art, the program operation can be executed by setting bit lines to a bit line bias voltage based on program data and then supplying a program voltage and a pass voltage to corresponding word lines of the selected memory block through selection lines. Generally, after the word lines are driven with the pass voltage during a word line enable interval, only a selected word line is driven with the program voltage during a program execution interval. After the program execution interval, it is determined whether all memory cells are programmed (Block 40). If the memory cells all are programmed, the program operation is ended. If one or more of the memory cells are not programmed, Blocks 30 and 40 are repeated within a predetermined program loop number.
A word line driving method according to the above program method is explained hereinafter with reference to FIG. 1B. First, a block word line BLKWL is driven with a high voltage in order to apply a program/pass voltage to a word line. Thus, a selection line Si and a word line WLi are electrically connected to each other through a switch transistor STi. Under this condition, the selection line Si is driven with the program/pass voltage by a pump in a high voltage generating circuit. In this case, the pump of the high voltage generating circuit may instantly charge every parasitic capacitance of the selection line Si and the word line WLi. This can be an obstacle to improving a program speed. Moreover, it takes longer time to charge a word line if the number of memory cells connected to the word line WLi is increased. Such a problem can be solved by increasing a pump capacity. But, this may result in increase in a chip area.